FYP Batch HITACHI & TOSHIBA FYP JD 2024 #21

 

FYP JD 2024 TOSHIBA JD 2024 #21     à NORHAIDA BINTI MUSTAFA

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Student : MUHAMMAD DANISH IHSAN BIN MOHD RIDZUWAN

Title :  Design and Verification of a Bit Zero Detector for Non-Volatile Memory Control using 16-Bit input in Mentor Graphics.

Objectives :

-To develop a bit zero detector using 16 bit input integrated with 0.13μm CMOS technology and SilTerra library components.

-To utilize Mentor Graphics tools for schematic design, layout creation, simulation, and verification.

-To optimize the zero detector's design for performance, power efficiency, and area utilization, ensuring compatibility with 0.13μm CMOS technology.

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Student : ADIB ALHAM BIN JAILANI

Title :  Design and Optimization of a Low-Power 8-Bit Synchronous Up-Down

Counter using 0.13 um CMOS Technology in Mentor Graphic Software

Objectives :

• To design an 8-bit synchronous up-down counter using 0.13um Silterra

Library.

•To analyze the impact of clock gating on power consumption

• To develop an optimized layout design to ensure optimal low power

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Student : MUHAMMAD IRFAN SHAHMI BIN SUPARDI

Title : DESIGN AND PERFORMANCE ANALYSIS OF AN 4-BIT BARREL SHIFTER WITH LOW POWER CONSUMPTION AND LOW DELAY TIME USING 0.13µM CMOS TECHNOLOGY IN MENTOR GRAPHIC SOFTWARE

Objectives :

-TO DESIGN AN 4-BIT BARREL SHIFTER USING 0.13µM CMOS TECHNOLOGY WITH SILTERRA LIBRARY IN MENTOR GRAPHICS SOFTWARE.

 

-TO ANALYZE THE PERFORMANCE OF THE BARREL SHIFTER IN TERMS OF POWER CONSUMPTION AND DELAY TIME.

 

-TO DEVELOP OPTIMISED LAYOUT DESIGN OF IMPROVED POWER CONSUMPTION  AND DELAY TIME FOR BARREL SHIFTER