Project Proposal Batch SANYO & SAKURAI JJ 2026 #13

 

Project Proposal Batch SANYO & SAKURAI JJ 2026 #13 --> NORHAFIZAN BINTI MOHD HANIB

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Student name : NUR AUNI INSYIRAH BINTI MOHD NAZRI

Title : Design and Analysis of 8-bit SRAM Architecture Using 250nm CMOS Technology

Objectives :

1. To design an 8-bit SRAM architecture using 250nm CMOS technology.

2. To simulate and verify the SRAM design using Siemens EDA.

3. To evaluate the performance in terms of power, delay and stability.

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Student name : ATIQAH DAMIA BINTI AHMAD FEISAL

Title : DESIGN AND IMPLEMENTATION OF 8-BIT PARITYGENERATOR USING SIEMENS EDA TOOLS

Objectives :

 

Design and simulate circuit schematics for 8-bit parity generator.

-Create layout design based on schematics and verify using LVS and DRC.

-Compare multiple designs to find most efficient design in terms of power consumption and area.

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Student name : MUHAMMAD ARIF DANIAL BIN AHMAD KAMIL 

Title : Design and Simulation of a High Performance 4-bit Magnitude Comparator Using 0.25µm CMOS Technology 

Objectives :

 

-To design a High Performance 4-Bit Magnitude Comparator using 0.25um CMOS Technology

- To perform a functional simulation using Siemens EDA tools

- To compare the improvement of 4- Bit Magnitude Comparator performance (delay) with the existed design

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Student name : ZULHILMI IRFAN BIN MD ARIFF @ FADILAH

Title : DESIGN OF LOW POWER 4-BIT PRIORITY ENCODER USING 250nm CMOS TECHNOLOGY WITH SIMULATION AND VERIFICATION PERFORMED IN SIEMENS EDA.

Objectives :

 

-TO DESIGN AND IMPLEMENT THE TRANSISTOR LEVEL CMOS SCHEMATIC OF PRIORITY ENCODER USING 250nm TECHNOLOGY

-TO COMPARE THE PROPOSED LOW POWER DESIGN WITH A CONVENTIONAL CMOS IMPLEMENTATION

-TO PEFORM FUNCTIONAL SIMULATION USING SIEMENS EDA TOOLS

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Student name : MUHAMAD ISMAEL BIN FAIZAL AMIMI 

Title : DESIGN AND IMPLEMENTATION OF A HIGH SPEED AND LOW POWER 8 BIT PARITY CHECKER WITH 0.25um CMOS TECHNOLOGY

Objectives :

 

TO DESIGN AND IMPLEMENT THE TRANSISTOR LEVEL CMOS SCHEMATIC OF A HIGH SPEED AND LOW POWER 8 BIT PARITY CHECKER USING 0.25um TECHNOLOGY.

TO PERFORM A FUNCTIONAL SIMULATION USING SIEMENS EDA TOOLS.

TO COMPARE THE PURPOSED LOW POWER AND HIGH SPEED DESIGN WITH CMOS IMPLEMENTATION.

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